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Pin Configuration
PGOOD
EN
FB
VOUT
A1
A2
A3
A4
A4
A3
A2
A1
MODE
GND
B1
C1
B2
C2
B3
C3
B4
C4
B4
C4
B3
C3
B2
C2
B1
C1
VIN
SW
D1
E1
D2
E2
D3
E3
D4
E4
D4
E4
D3
E3
D2
E2
D1
E1
Pin Definitions
Figure 2. Top View
Figure 3. Top View Bottom View
Bump #
A1
A2
A3
A4
B1
B2, B3,
C1 – C4
B4
D1, D2,
E1, E2
D3, D4,
E3, E4
Name
PGOOD
EN
FB
VOUT
MODE
GND
AGND
VIN
SW
Description
Power Good . This open-drain pin pulls LOW if the output falls out of regulation or is in soft-start.
Enable . The device is in Shutdown Mode when this pin is LOW. Do not leave this pin floating. When
tying HIGH, use at least a 1 k ? series resistor if V IN is expected to exceed 4.5 V.
FB . Connect to resistor divider. The IC regulates this pin to 0.8 V.
VOUT . Sense pin for V OUT . Connect directly to C OUT .
MODE / SYNC . A logic 0 allows the IC to automatically switch to PFM during light loads. When held
HIGH, the IC to stays in PWM Mode. The regulator also synchronizes its switching frequency to four
times (4X) the frequency provided on this pin (f MODE ). Do not leave this pin floating. When tying HIGH,
use at least a 1 k ? series resistor if V IN is expected to exceed 4.5 V.
Ground . Low-side MOSFET is referenced to this pin. C IN and C OUT should be returned with a minimal
path to these pins.
Analog Ground . All signals are referenced to this pin. Avoid routing high dV/dt AC currents through
this pin.
Power Input Voltage . Connect to input power source. Connect to C IN with minimal path.
Switching Node . Connect to inductor.
? 2011 Fairchild Semiconductor Corporation
FAN53540 ? Rev. 1.0.3
3
www.fairchildsemi.com
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